Due to the diverse processing behavior and unpredictable nature of the next generation applications future embedded devices may no longer perform efficiently when following current trends, e.g. when a design is tailor made for a specific scenario or application domain. We believe that crucial design decisions can no longer be fixed/determined at design time. This begets the demand for an innovative processor architecture reacting flexibly to the run-time scenarios. Therefore we propose a novel multi-grained reconfigurable hardware architecture, tightly integrating coarse and fine-grained reconfigurable fabrics extended by the capability to handle different Instruction Set Architectures (ISAs) in parallel. A flexible software framework is needed to make use of the novel features of the proposed architecture. Different ISAs require an Architecture Description Language based, retargetable compilation framework while automatic multi-grained Custom Instruction detection will deliver optimized implementations for our multi-grained reconfigurable hardware accelerators. Additionally, an adaptive runtime system is required to efficiently distribute the available hardware resources between different applications and threads considering performance and power constraints. We believe that our novel concept will provide a promising paradigm for adaptive embedded processing, targeting next generation applications and design-time unpredictable behavior.